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cy23fp12-002 200-mhz field programmable zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07644 rev. *b revised january 18, 2011 features pre-programmed configuration fully field-programmable ? input and output dividers ? inverting/noninverting outputs ? phase-locked loop (pll) or fanout buffer configuration 10 mhz to 200 mhz operating range split 2.5-v or 3.3-v outputs two low-voltage complementary metal oxide semiconductor (lvcmos) reference inputs twelve low-skew outputs ? output-output skew < 200 ps ? device-device skew < 500 ps input-output skew < 250 ps cycle-cycle jitter < 100 ps (typical) three-stateable outputs less than 50 a shutdown current spread aware ? 28-pin shrunk small outline package (ssop) 3.3-v operation functional description the cy23fp12-002 is a pre-programmed version of the cy23fp12. it features a high-performance fully field-program- mable 200-mhz zero delay buffer designed for high-speed clock distribution. the integrated p ll is designed for low jitter and optimized for noise rejection. these parameters are critical for reference clock distribution in systems using high-performance asics and microprocessors. the cy23fp12-002 is fully programmable through volume or prototype programmers, enabling the user to define an application-specific zero delay buffer with customized input and output dividers, feedback topology (internal/external), output inversions, and output drive str engths. for additional flexibility, the user can mix and match multiple functions, listed in table 2 on page 5, and assign a particular function set to any one of the four possible s1-s2 control bit combinations. this feature enables the implementation of four distinct personalities, selectable with s1-s2 bits, on a single programmed silicon. the cy23fp12-002 also features a proprietary auto power down circuit that shuts down the devi ce in case of a ref failure, resulting in less than 50 a of current draw. the cy23fp12-002 provides 12 outputs grouped in two banks with separate power supply pins which can be connected independently to either a 2.5 v or a 3.3 v rail. selectable reference input is a fault tolerance feature which allows for glitch-free switch over to secondary clock source when refsel is asserted/deasserted. fbk m n 100 to 400mhz pll clka1 clka3 clka2 ref2 refsel clka4 clka5 clkb1 clkb3 clkb2 clkb4 clkb5 vdda vssa vddb v ss b 2 3 4 x clka0 vddc vssc 1 lock detect test logic ref1 clkb0 s [ 2:1 ] function selection 2x logic block diagram [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 2 of 14 contents pin configuration ............................................................. 3 pin description ................................................................. 3 field programming the cy23fp12-002 ...................... 7 cyberclocks ? software .............................................. 7 cy3672-usb development kit ................................... 7 cy23fp12-002 frequency calcul ation ........................... 7 absolute maximum conditions....................................... 8 operating conditions....................................................... 8 dc electrical specifications ............................................ 8 switching characteristics [5] .......................................... 9 switching waveforms .................................................... 10 ordering information...................................................... 11 ordering code definition........ ................................... 11 package drawing and dimension ................................. 12 acronyms ....................................... 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 14 worldwide sales and design supp ort............. .......... 14 products .................................................................... 14 psoc solutions ......................................................... 14 [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 3 of 14 pin configuration figure 1. 28-pin ssop pin description pin name i/o type description 1 ref2 i lvttl/lvcmos input reference frequency, 5v-tolerant input. 2 ref1 i lvttl/lvcmos input reference frequency, 5v-tolerant input. 3 clkb0 o lvttl clock output, bank b. 4 clkb1 o lvttl clock output, bank b. 5v ssb pwr power ground for bank b. 6 clkb2 o lvttl clock output, bank b. 7 clkb3 o lvttl clock output, bank b. 8v ddb pwr power 2.5-v or 3.3-v supply, bank b. 9v ssb pwr power ground for bank b. 10 clkb4 o lvttl clock output, bank b. 11 clkb5 o lvttl clock output, bank b. 12 v ddb pwr power 2.5-v or 3.3-v supply, bank b. 13 v ddc pwr power 3.3 v core supply. 14 s2 i lvttl select input. 15 s1 i lvttl select input. 16 v ssc pwr power ground for core. 17 v dda pwr power 2.5-v or 3.3-v supply, bank a. 18 clka5 o lvttl clock output, bank a. 19 clka4 o lvttl clock output, bank a. 20 v ssa pwr power ground for bank a. 21 v dda pwr power 2.5-v or 3.3-v supply bank a. 22 clka3 o lvttl clock output, bank a. 23 clka2 o lvttl clock output, bank a. 24 v ssa pwr power ground for bank a. 25 clka1 o lvttl clock output, bank a. 26 clka0 o lvttl clock output, bank a. 27 fbk i lvttl pll feedback input. 28 refsel i lvttl reference select in put. when refsel = 0, ref1 is selected. when refsel = 1, ref2 is selected. 21 28 refsel fbk clka0 clka1 v ssa clka2 clka3 v dda 1 2 3 4 5 6 7 8 22 23 24 25 26 27 ref2 ref1 clkb0 clkb1 v ssb clkb2 clkb3 v ddb 17 v dda 20 v ssa 19 clka4 18 clka5 16 v ssc 15 s1 9 v ssb 12 v ddb 13 v ddc 10 clkb4 11 clkb5 14 s2 [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 4 of 14 figure 2. basic pll block diagram following is a list of independent functions that can be programm ed with a volume or prototype programmer on the ?pre-programme d? silicon. table 1. programmable functions configuration description default dc drive bank a programs the dr ive strength of bank a outputs. the user can select one out of two possible drive strength settings that produce output dc currents in the range of 16 ma to 20 ma. + 20 ma dc drive bank b programs the dr ive strength of bank b outputs. the user can select one out of two possible drive strength settings that produce output dc currents in the range of 16 ma to 20 ma. + 20 ma output enable for bank b clocks enables/disables clkb[5:0] outputs. each of the six outputs can be disabled individually if not used, to minimize electromagnetic interference (emi) and switching noise. enable output enable for bank a clocks enables/disables clka[5:0] outputs. each of the six outputs can be disabled individually if not used, to minimize emi and switching noise. enable inv clka0 generates an inverted clock on the clka0 output. when this option is programmed, clka0 and clka1 will become complimentary pairs. non invert inv clka2 generates an inverted clock on the clka2 output. when this option is programmed, clka2 and clka3 will become complimentary pairs. non invert inv clka4 generates an inverted clock on the clka4 output. when this option is programmed, clka4 and clka5 will become complimentary pairs. non invert inv clkb0 generates an inverted clock on the clkb0 output. when this option is programmed, clkb0 and clkb1 will become complimentary pairs. non invert /1,/2,/3,/4, /x,/2x /1,/2,/3,/4, /x,/2x /1,/2,/3,/4, /x,/2x /1,/2,/3,/4, /x,/2x /1,/2,/3,/4, /x,/2x /1,/2,/3,/4, /x,/2x pll /m /n output function select matrix ref fbk clkb5 clkb4 clkb3 clkb2 clkb1 clkb0 clka5 clka4 clka3 clka2 clka1 clka0 [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 5 of 14 the following table lists independent functions, which can be assign ed to each of the four s1 and s2 combinations. when a parti cular s1 and s2 combination is selected, the dev ice assumes the configuration (which is essentially a set of functions given in table 2 ) that has been preassigned to that particular combination. inv clkb2 generates an inverted clock on the clkb2 output. when this option is programmed, clkb2 and clkb3 will become complimentary pairs. non-invert inv clkb4 generates an inverted clock on the clkb4 output. when this option is programmed, clkb4 and clkb5 will become complimentary pairs. non-invert pull down enable enables/disables internal pulldowns on all outputs enable fbk pull down enable enables/disables internal pulldowns on the feedback path (applicable to both internal and external feedback topologies) enable fbk sel selects between the internal and the external feedback topologies internal table 2. programmable func tions for s1/s2 combinations function description default output enable clkb[5:4] enables/di sables clkb[5:4] output pair enable output enable clkb[3:2] enables/di sables clkb[3:2] output pair enable output enable clkb[1:0] enables/di sables clkb[1:0] output pair enable output enable clka[5:4] enables/di sables clka[5:4] output pair enable output enable clka[3:2] enables/di sables clka[3:2] output pair enable output enable clka[1:0] enables/di sables clka[1:0] output pair enable auto power down enable enables/disables the auto power down circuit, which monitors the reference clock rising edges and shuts down the device in case of a reference ?failure.? this failure is triggered by a drift in reference frequency below a set limit. this auto power down circuit is disabled internally when one or more of the ou tputs are configured to be driven directly from the reference clock. enable pll power down shuts down the pll when the device is configured as a non-pll fanout buffer. see table 4 on page 6 m[7:0] assigns an eight-bit value to reference divider ?m. the divider can be any integer value from 1 to 256; however, the pll input frequency cannot be lower than 10 mhz. see ta b l e 4 on page 6 n[7:0] assigns an eight-bit value to feedback divider ?n. the divider can be any integer value from 1 to 256; however, the pll input frequency cannot be lower than 10 mhz. see ta b l e 4 on page 6 x[6:0] assigns a seven-bit value to output divi der ?x. the divider can be any integer value from 5 to 130. divide by 1,2,3, and 4 are preprogramm ed on the device and can be activated by the appropriate output mux setting. see ta b l e 4 on page 6 divider source selects between the pll output and the reference clock as the source clock for the output dividers. see ta b l e 4 on page 6 clka54 source independently selects one out of the eight possible output dividers that will connect to the clka5 and clka4 pa ir. please refer to table 3 on page 6 for a list of divider values. see ta b l e 4 on page 6 clka32 source independently selects one out of the eight possible output dividers that will connect to the clka3 and clka2 pa ir. please refer to table 3 on page 6 for a list of divider values. see ta b l e 4 on page 6 clka10 source independently selects one out of the eight possible output dividers that will connect to the clka1 and clka0 pa ir. please refer to table 3 on page 6 for a list of divider values. see ta b l e 4 on page 6 clkb54 source independently selects one out of the eight possible output dividers that will connect to the clkb5 and clkb4 pa ir. please refer to table 3 on page 6 for a list of divider values. see ta b l e 4 on page 6 clkb32 source independently selects one out of the eight possible output dividers that will connect to the clkb3 and clkb2 pa ir. please refer to table 3 on page 6 for a list of divider values. see ta b l e 4 on page 6 clkb10 source independently selects one out of the eight possible output dividers that will connect to the clkb1 and clkb0 pa ir. please refer to table 3 on page 6 for a list of divider values. see ta b l e 4 on page 6 table 1. programmable functions (continued) configuration description default [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 6 of 14 ta b l e 3 is a list of output dividers that are independent ly selected to connect to each output pair. in the default (pre-programmed) st ate of the device, s1 and s2 pins will function as indicated in ta b l e 4 . the cy23fp12-002 can be programmed to other configurations. table 3. output dividers clka/b source output connects to 0 [000] ref 1 [001] divide by 1 2 [010] divide by 2 3 [011] divide by 3 4 [100] divide by 4 5 [101] divide by x 6 [110] divide by 2x [1] 7 [111] test mode [lock signal] [2] table 4. pre-programmed configuration outputs s2, s1 divsrc example output ref input (mhz) vco (mhz) output (mhz) clka0, a1 00 1 25 200 200 clka2, a3 00 3 25 200 66.7 clka4, a5 00 x=6 25 200 33.3 clkb0, b1 00 x=6 25 200 33.3 clkb2, b3 00 4 25 200 50 clkb4, b5 00 ref 25 200 25 clka0, a1 01 4 100 200 50 clka2, a3 01 4 100 200 50 clka4, a5 01 4 100 200 50 clkb0, b1 01 4 100 200 50 clkb2, b3 01 x=8 100 200 25 clkb4, b5 01 x=8 100 200 25 clka0, a1 10 x=8 33.3 266.6 33.3 clka2, a3 10 x=8 33.3 266.6 33.3 clka4, a5 10 x=8 33.3 266.6 33.3 clkb0, b1 10 4 33.3 266.6 66.6 clkb2, b3 10 4 33.3 266.6 66.6 clkb4, b5 10 4 33.3 266.6 66.6 clka0, a1 11 ref 100 powerdown 100 clka2, a3 11 ref 100 powerdown 100 clka4, a5 11 ref 100 powerdown 100 clkb0, b1 11 2 100 powerdown 50 clkb2, b3 11 2 100 powerdown 50 clkb4, b5 11 2 100 powerdown 50 notes 1. outputs will be rising edge aligned only to those outputs using this same device setting. 2. when the source of an output pair is set to [111], the output pair becomes lock indicator signal. for example, if the source of an output pair (clka0, clka1) is set to [111], the clka0 and clka1, becomes lock indicator signals. in non-invert mode, clka0 and clka1 signals will be high when th e pll is in lock mode. if clka0 is in an invert mode, the clka0 will be low and the clka1 will be high when the pll is in lock mode. [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 7 of 14 field programming the cy23fp12-002 the cy23fp12-002 comes pre-programmed and ready for use, but it can also be reprogrammed to any other valid configuration. when programming, it must be programmed in a device programmer prior to being inst alled in a circuit. the cy23fp12-002 is based on flash te chnology, so it can be repro- grammed up to 100 times. this enables fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. samples and small prototype q uantities can be programmed on the cy3672-usb programmer. cypress?s value-added distri- bution partners and third-party programming systems from bp microsystems, hilo systems, and others are available for large production quantities. cyberclocks ? software cyberclocks is an easy-to-use soft ware applicatio n that allows the user to custom-configure the cy23fp12-002. users can specify the ref, pll frequenc y, output frequencies and/or post-dividers, and different functional options. cyberclocks outputs an industry standard jedec file used for programming the cy23fp12-002. cyberclocks can be downloaded free of charge from the cypress website at www.cypress.com . cy3672-usb development kit the cypress cy3672-usb developer kit , in combination with the cy3692 socket adapter, is used to program samples and small prototype quantit ies of the cy23fp12-002. this portable programmer connects to a pc through a usb interface. the jedec file output of cyberclocks can be downloaded to the portable programmer for small-vo lume programming, or for use with a production programming system for larger volumes. cy23fp12-002 frequency calculation the cy23fp12-002 is an extremely flexible clock buffer with up to 12 individual outputs, generat ed from an integrated pll. four variables are used to determine the final output frequency. these are the input reference frequency, the m and n dividers, and the post divider. the basic pll block diagram is shown in figure 2 on page 4. each of the six clock output pair s has many post divider options available to it. x is a programmable value between 5 and 130, and 2x is twice that value. ther e are six post divider options: /1, /2, /3, /4, /x, and /2x. the post divider options can be applied to the calculated pll frequency or to the ref directly. the feedback is connected either internally to clka0 or externally to any output. a programmable divider, m, is inserted between the reference input, ref, and the phase detector. the divider m can be any integer 1 to 256. the pll input frequency cannot be lower than 10 mhz or higher than 200 mhz. a programmable divider, n, is inserted between the feedback input, fbk, and the phase detector. the divider n can be any integer 1 to 256. the pll input frequency cannot be lower than 10 mhz or higher than 200 mhz. the output can be calculated as follows: f ref / m = f fbk / n. f pll = (f ref * n * post divider) / m. f out = f pll / post divider. in addition to above divider options, another option bypasses the pll and passes the ref di rectly to the output. f out = f ref . [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 8 of 14 absolute maximum conditions exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. parameter description condition min. max. unit v dd supply voltage nonfunctional ?0.5 7 vdc v in input voltage ref relative to v cc ?0.5 v dd + 0.5 vdc v in input voltage except ref relative to v cc ?0.5 v dd + 0.5 vdc lu i latch up immunity functional 300 ma t s temperature, storage nonfunctional ?65 125 c t j junction temperature ? 125 c ? jc dissipation, junction to case functional 34 c/w ? ja dissipation, junction to ambient functional 86 c/w esd h esd protection (human body model) 2000 v m sl moisture sensitivity level msl ? 1 class g ates total functional gate count assembled die 21375 each ul?94 flammability rating at 1/8 in. v?0 class fit failure in time manufacturing test 10 ppm operating conditions parameter description test conditions min. max. unit v ddc core supply voltage 3.135 3.465 v v dda , v ddb bank a, bank b supply voltage 3.135 3.465 v 2.375 2.625 v t a temperature, operating ambient commercial temperature 0 70 c t pu power-up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms notes 3. applies to both ref clock and fbk. 4. parameter is guaranteed by design and charac terization. not 100% tested in production. dc electrical specifications parameter description test conditions min. typ. max. unit v il input low voltage [3] ? ? 0.3 v dd v v ih input high voltage [3] 0.7 v dd ??v i il input low current [3] v in = 0 v ? ? 50 a i ih input high current [3] v in = v dd ??50 a v ol output low voltage [4] v dda /v ddb = 3.3 v, i ol = 16 ma (standard drive) v dda /v ddb = 3.3 v, i ol = 20 ma (high drive) v dda /v ddb = 2.5 v, i ol = 16 ma (high drive) ??0.5v v oh output high voltage [4] v dda /v ddb = 3.3 v, i oh = ?16 ma (standard drive) v dda /v ddb = 3.3 v, i oh = ?20 ma (high drive) v dda /v ddb = 2.5 v, i oh = ?16 ma (high drive) v dd ? 0.5 ? ? v i dds power-down supply current ref = 0 mhz ? 12 50 a i dd supply current v dda = v ddb = 2.5 v, unloaded outputs at 166 mhz ? 40 65 ma v dda = v ddb = 2.5 v, loaded outputs at166 mhz, c l = 15 pf ?65100 v dda = v ddb = 3.3 v, unloaded outputs at 166 mhz ? 50 80 v dda = v ddb = 3.3 v, loaded outputs at 166 mhz, c l = 15 pf ?100120 [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 9 of 14 switching characteristics [5] parameter description test conditions min typ max unit f ref reference frequency [6] 10 ? 200 mhz er ref reference edge rate 1 ? ? v/ns dc ref reference duty cycle 25 ? 75 % f out output frequency [7] c l = 15 pf 10 ? 200 mhz c l = 30 pf 10 ? 100 dc out output duty cycle [5] v dda/b = 3.3 v, measured at v dd /2 45 50 55 % v dda/b = 2.5 v, measured at v dd /2 40 50 60 t 3 rise time [5] v dda/b = 3.3 v, 0.8 v to 2.0 v, c l = 30 pf (standard drive and high drive) ??1.6ns v dda/b = 3.3 v, 0.8 v to 2.0 v, c l = 15 pf (standard drive and high drive) ??0.8 v dda/b = 2.5 v, 0.6 v to 1.8 v, c l = 30 pf (high drive only) ??2.0 v dda/b = 2.5 v, 0.6 v to 1.8 v, c l = 15 pf (high drive only) ??1.0 t 4 fall time [5] v dda/b = 3.3 v, 0.8 v to 2.0 v, c l = 30 pf (standard drive and high drive) ??1.6ns v dda/b = 3.3 v, 0.8 v to 2.0 v, c l = 15 pf (standard drive and high drive) ??0.8 v dda/b = 2.5 v, 0.6 v to 1.8 v, c l = 30 pf (high drive only) ??1.6 v dda/b = 2.5 v, 0.6 v to 1.8 v, c l = 15 pf (high drive only) ??0.8 ttb total timing budget, [8,9] bank a and b same frequency outputs at 200 mhz, tracking skew not included ? ? 650 ps total timing budget, bank a and b different frequency ? ? 850 t 5 output-to-output skew [5] all outputs equally loaded ? ? 200 ps bank-to-bank skew same frequency ? ? 200 bank-to-bank skew different frequency ? ? 400 bank-to-bank skew different voltage, same frequency ? ? 400 t 6 input-to-output skew (static phase offset) [5] measured at v dd /2, ref to fbk ? 0 250 ps t 7 device-to-device skew [5] measured at v dd /2 ? 0 500 ps t j cycle-to-cycle jitter [5] (peak-to-peak) bank a and b same frequency ? ? 200 ps cycle-to-cycle jitter [[5] (peak-to-peak) bank a and b different frequency ? ? 400 notes 5. all parameters are specified with loaded outputs. 6. when the device is configured as a non-pll fanout buffer (pll power down enabled), the reference frequency can be lower than 10mhz. with auto power down disabled and pll power down enabled, the reference frequency can be as low as dc level. 7. when the device is configured as a non-pll fanout buffer (pll power down enabled), the output frequency can be lower than 10m hz. with auto power down disabled and pll power down enabled, the out put frequency can be as low as dc level. 8. guaranteed by statistical correlation. tested initially and af ter any design or process changes that may affect these paramet ers. 9. ttb is the window between the earliest and the latest output clocks with respect to the input reference clock across variatio ns in output frequency, supply voltage, operating temperature, input clock edge rate, and process. the me asurements are taken with the ac test load specified and inclu de output-output skew, cycle-cycle jitter, and dynamic phase error.ttb will be equal to or smaller than the maximum specified value at a given frequen cy. [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 10 of 14 switching waveforms figure 3. duty cycle timing figure 4. all outputs rise/fall time figure 5. output-output skew figure 6. input-output propagation delay t tsk tracking skew input reference clock at < 50-khz modulation with 3.75% spread ? ? 200 ps t lock pll lock time [5] stable power supply, valid clock at ref ? ? 1.0 ms t ld inserted loop delay max loop delay for pll lock (stable frequency) ?? 7ns max loop delay to meet tracking skew spec ? ? 4 ns switching characteristics (continued) [5] parameter description test conditions min typ max unit [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 11 of 14 figure 7. device-device skew ordering code definition test circuits ordering information ordering code package type operating range pb-free cy23fp12oxc-002 28-pin ssop commercial, 0 c to 70 c cy23fp12oxc-002t 28-pin ssop ? tape and reel commercial,0 c to 70 c programmer cy3672-usb programmer with usb interface cy3692 cy23fp12 socket adapter for cy3672-usb programmer (label cy3672 adp006) package type: t = tape and reel, blank = tube temperature code: c = commercial, i = industrial package: 28-pin ssop, pb-free device number cy23fp12 ox x (t) [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 12 of 14 package drawing and dimension figure 8. 28-pin (5.3 mm) shrunk small outline package 51-85079 *d [+] feedback
cy23fp12-002 document #: 38-07644 rev. *b page 13 of 14 acronyms document conventions units of measure acronym description dcxo digitally controlled crystal oscillator esd electrostatic discharge pll phase locked loop rms root mean square ssop shrunk small outline package xtal crystal symbol unit of measure c degree celsius a micro amperes ma milli amperes ms milli seconds mhz mega hertz ns nano seconds pf pico farad ps pico seconds vvolts [+] feedback
document #: 38-07644 rev. *b revised january 18, 2011 page 14 of 14 cyberclocks? is a trademark and cyclocks is a registered trademark of cypress semi conductor corporation. purchase of i 2 c components from cypress or one of its sublicensed associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp semiconductors. all products and company names mentioned in this document may be the tradem arks of their respective holders. cy23fp12-002 ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: cy23fp12-002 200-mhz field programmable zero delay buffer document number: 38-07644 rev. ecn no. submission date orig. of change description of change ** 206761 see ecn rgl new data sheet *a 2865396 01/25/2010 kvm updated template. removed references to industrial temperature range added captions to tables 1-4. added operating conditions table. various edits to text. removed ?ftg? from text about the cy3672 programmer. added part numbers cy23fp12 oxc-002, cy23fp12oxc-002t removed part numbers cy23fp 12oc-002, cy23fp12oc-002t, cy23fp12oi-002 a nd cy23fp12oi-002t changed part number cy3672 to cy3672-usb. updated package drawing. *b 3146346 01/18/2 011 bash modified vin max value from 7 to v dd + 0.5 in absolute maximum conditions . added acronyms , document conventions , and ordering code definition [+] feedback

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